1. Field of the Invention
The present invention relates to a DMA (Direct Memory Access) controller performing controls such as direct data transfer between memories not through a CPU (Central Processing Unit). More particularly, the present invention relates to a DMA controller in which a bus access ratio can be set.
2. Description of the Background Art
Recently, as a greater number of information processing apparatuses such as personal computers are used, these apparatuses are required to operate at higher processing speed and provide greater functionality. Examples of features for increasing the processing speed of such information processing apparatuses include DMA that provides for direct data transfer between memories not through a CPU. The structure and operation of a conventional DMA controller will be described in the following.
Structure of conventional DMA Controller
FIG. 1 is a block diagram showing a general structure of a conventional DMA controller. The DMA controller includes: a source address register 10 storing a source address for DMA; a destination address register 11 storing a destination address for DMA; a DMA transfer counter 12 storing a number of transfers of DMA; a DMA request selecting register 13 selecting a request signal for DMA; a DMA controlling portion 50 accessing an external memory (not shown) for DMA transfer; a DMA request detecting portion 60 detecting an externally applied DMA request in accordance with the settings of DMA request selecting register 13; and a bus access request controlling portion 70 requesting a bus arbiter (not shown) a permission to use a bus in response to the bus access request from DMA controlling portion 50.
Signals 100 to 104 shown on the left side of the DMA controller are used by an external bus master such as a CPU in accessing source address register 10, destination address register 11, DMA transfer counter 12 or DMA request selecting register 13. These signals are: a chip select (CS) signal 100 indicating as to if access is valid; 32 address (ADDR) signals 101 selecting a register to be accessed; a read/write control (R/W) signal 102 indicating if the access is read or write access; 32 write data (WDATA) signals 103 transferring data for write access; and 32 read data (RDATA) signals 104 transferring data for read access.
Signals 110 to 114 shown on the right side of the DMA controller are used by DMA controlling portion 50 in accessing the external memory (not shown). These signals are: 32 address (ADDR) signals 110 selecting a region to be accessed; a read/write control (R/W) signal 111 indicating if access is read or write access; 32 write data (WDATA) signals 112 transferring data for write access; 32 read data (RDATA) signals 113 transferring data for read access; and a ready (READY) signal 114 indicating the completion of bus access.
Other signals used are: a DMA request (DMAREQ) signal 120 accepting an externally applied DMA request; a bus access request (BUSREQ) signal 130 to the bus arbiter (not shown); a bus access granting (BUSGNT) signal 131 from the bus arbiter; and a clock (CLK) signal 150 generally used for a system.
DMA request detecting portion 60 detects the rise of a signal selected by DMA request selecting register 13 among 32 DMAREQ signals 120 and stores in an internal register (not shown) the fact that there is a DMA request from an external portion. DMA request detecting portion 60 outputs a DMA request (dmrq) to DMA controlling portion 50 when the internal register is set. DMA request detecting portion 60 resets the above mentioned internal register when a DMA acknowledgement (dmack) is output from DMA controlling portion 50. Bus access request controlling portion 70 asserts BUSREQ signal 130 when a DMA enable (dmen) signal is output from DMA controlling portion 50.
FIG. 2 is a block diagram used for describing in greater detail the structure of DMA controlling portion 50. DMA controlling portion 50 includes: a source address counter 251 of a 32-bit counter calculating a source address; a destination address counter 252 of a 32-bit counter calculating a destination address; a transfer counter 253 of a 16-bit counter for calculating a transferred data amount; a state machine (FSM) 254 generating and outputting a control signal depending on the state of data transfer by DMA; an address generating portion 255 generating and outputting an ADDR signal 110 based on outputs from source address counter 251 and destination address counter 252; and a write data generating portion 256 generating and outputting a WDATA signal 112.
FSM 254 generates and outputs a DMA acknowledgement (dmack) signal, destination address setting (saset) signal, read completion (rdcmp) signal, DMA enable (dmen) signal, write completion (wrcmp) signal and RIW signal 111. FSM 254 will later be described in greater detail.
When dmack is asserted, a value (sa) that has been set in source address register 10 is set in source address counter 251. When rdcmp is asserted, the value of source address counter 251 is increased by 4, but the current value is maintained in other cycles.
When dmack is asserted, a value (da) that has been set in destination address counter 11 is set in destination address counter 252. When wrcmp is asserted, the value of destination address counter 252 is increased by 4, but the current value is maintained in other cycles.
When dmack is asserted, a value (tr) that has been set in DMA transfer counter 12 is set in transfer counter 253. When wrcmp is asserted, the value of transfer counter 253 is decreased by 1, but the current value is maintained in other cycles.
FIG. 3 is a block diagram used for describing the structure of write data generating portion 256 in greater detail. Write data generating portion 256 includes selectors 301 and 302, flip-flops 303 and 304, and an AND circuit 305. Note that selector 302 and flip-flop 304 both have a 32-bit width.
When READY is asserted, selector 301 selects and outputs rdcmp. At the time, if rdcmp is asserted, flip-flop 303 holds and outputs xe2x80x9cHxe2x80x9d at the rise of a CLK signal. When READY is asserted next time, AND circuit 305 outputs xe2x80x9cHxe2x80x9d and selector 302 selects and outputs the value of RDATA 113. Flip-flop 304 holds the value of RDATA 113 at the rise of CLK for outputting it as WDATA 112.
FIG. 4 is a diagram showing state transitions of FSM 254. Circles represent states, whereas arrows represent state transitions. Transition conditions are shown next to the arrows representing the state transitions. If none of the transition conditions is met, FSM 254 is maintained in the current state. FSM 254 is initially set in an IDLE state. Note that, in the state transition diagram, xe2x80x9cand,xe2x80x9d xe2x80x9c|,xe2x80x9d and xe2x80x9c!xe2x80x9d respectively represent a logical product, logical addition and negation.
Outputs from FSM 254 are a dmen signal, dmack signal, saset signal, R/W signal 111, rdcmp signal, and wrcmp signal. The dmen signal is negated in the IDLE state, and asserted in all the other states. The dmack signal is asserted only in transition from the idle state to a BUSREQ1 state, and negated in all other states. The saset signal is asserted only in transition from the BUSREQ1 state to an RD state, and negated in all the other states. R/W 111 indicates write in WR state, and read in all the other states. The rdcmp signal is asserted only in transition from the RD state to a BUSREQ2 state or WR state, and negated in all the other states. The wrcmp is asserted only in transition from the WR state to the IDLE state, BUSREQ1 state or RD state, and negated in all the other states.
Operation of Conventional DMA Controller
(1) Settings of DMA
DMA is set when an external CPU writes values to internal registers (source address register 10, destination address register 11, DMA transfer counter 12 and DMA request selecting register 13 of the DMA controller).
FIG. 5 is a timing chart when the external CPU writes values to the internal registers of the DMA controller. At the rise of CLK signal 150 in a cycle 1, the internal register captures a value of ADDR signal 101 upon detection of a fact that CS signal 100 and R/W signal 102 are respectively at xe2x80x9cHxe2x80x9d and xe2x80x9cL.xe2x80x9d Based on a decoded result of ADDR signal 101, it is determined which register is to be accessed. Then, at the rise of CLK signal 150 in a cycle 2, a value of WDATA signal 112 is written to the register selected by the captured address.
Source and destination addresses for DMA are respectively set in source address register 10 and destination address register 11, and a transfer frequency of data transferred by DMA is set in DMA transfer counter 12. Further, bits of DMA request selecting register 13 respectively correspond to 32 DMAREQ signals 120, and xe2x80x9c1xe2x80x9d is set to the bit corresponding to the signal starting DMA.
(2) Start of DMA
DMA transfer is started when DMA request detecting portion 60 asserts dmrq at the rise of the signal corresponding to the bit of DMA request selecting register 13 in which xe2x80x9c1xe2x80x9d is set among DMA request signals 120.
(3) Execution of DMA
When DMA request detecting portion 60 asserts dmrq, DMA controlling portion 50 executes DMA transfer. FIG. 6 is a timing chart during DMA transfer. The states and outputs of the FSM in each cycle are denoted below the timing chart. Note that xe2x80x9c0xc3x970xe2x80x9d is set in source address register 10, xe2x80x9c0xc3x97100xe2x80x9d set in destination address register 11, and xe2x80x9c0xc3x9710xe2x80x9d in DMA transfer counter 12.
A cycle 0 corresponds to the IDLE state. When DMA request detecting portion 60 asserts dmrq in cycle 0, FSM 254 asserts dmack and is brought into the BUSREQ1 state. At the time, the values of source address register 10 and destination address register 11 are respectively set in source address counter 251 and destination address counter 252, and the value of DMA transfer counter 12 is set in transfer counter 253.
Since FSM 254 is brought into the state other than the IDLE state after cycle 1, it asserts dmen. In cycle 1 (BUSREQ1 state), FSM 254 asserts dmen, whereby bus access request controlling portion 70 asserts BUSREQ signal 130. In cycle 2 (BUSREQ1 state), BUSGNT and READY signals are asserted, so that FSM 254 is brought into the RD state. At the time, FSM 254 asserts saset. Address generating portion 255 detects a fact that saset has been asserted for outputting the value (0xc3x970) of source address counter 251 to ADDR signal 110.
In a cycle 3 (RD state), FSM 254 is brought into the WR state since BUSGNT and READY signals are asserted. At the time, FSM 254 asserts rdcmp, so that the value of source address counter 251 is increased by 4. Address generating portion 255 detects a fact that rdcmp has been asserted for outputting the value (0xc3x97100) of source address counter 252 to ADDR signal 110.
In a cycle 4 (WR state), FSM 254 sets R/W signal 111 in a writing state. In a cycle 5 (WR state), BUSGNT and READY signals are asserted and the value of a transfer counter 253 is xe2x80x9c0xc3x9710,xe2x80x9d so that FSM 254 is brought into the RD state. At the time, FSM 254 asserts wrcmp, so that the value of transfer address counter 252 is increased by 4 and that of transfer counter 253 is decreased by 1. Address generating portion 255 detects a fact that wrcmp has been asserted for outputting the value (0xc3x974) to ADDR signal 110. Write data generating portion 256 captures the value of RDATA signal 113 for outputting it to WDATA signal 112.
In and following a cycle 6, FSM 254 repeats the operation similar to that in cycles 3 to 5, in which FSM 254 is brought into the IDLE state and negates dmen when BUSGNT and READY are asserted and the value of transfer counter 253 is xe2x80x9c0xc3x971.xe2x80x9d Bus access request controlling portion 70 detects a fact that dmen has been negated, negates BUSREQ signal 130, and ends DMA transfer.
In the above described conventional DMA controller, however, a ratio of a bus access frequency of the DMA controller in the process of DMA transfer to a bus access frequency of another bus master such as a CPU cannot be controlled. Therefore, it is difficult to predict a band which allows another bus master to use the bus during DMA transfer. Further, a smooth process by another bus master may not be achieved due to DMA transfer with less urgency, or another bus master frequently accesses during DMA transfer with urgency. As a result, a problem arises which is associated with a loss of transfer data or degradation of the performance of the system as a whole.
An object of the present invention is to provide a DMA controller capable of predicting a band which allows another bus master to use a bus during DMA transfer.
Another object of the present invention is to provide a DMA controller capable of avoiding degradation of the performance of a system as a whole.
According to one aspect of the present invention, the DMA controller includes: a register for setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a counter counting the bus access frequency in accordance with the ratio set in the register; a bus access request controlling portion controlling a bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling DMA transfer in accordance with a bus access permission.
The bus access request controlling portion controls the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter. Thus, the ratio of the bus access frequency of DMA transfer to the bus access frequency of another bus master equals to the ratio set in the register, whereby a band which allows another bus master to use a bus during DMA transfer can be predicted. Further, the values set in the register can be appropriately varied depending upon the urgency of the DMA transfer, so that degradation of the performance of a system as a whole would not occur.
According to another aspect of the present invention, the DMA transfer method includes steps of: setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; detecting a DMA request; counting the bus access frequency in accordance with the set ratio; controlling a bus access request based on the detected DMA request and the counted result; and controlling DMA transfer in accordance with a bus access permission.
The bus access request is controlled based on the detected DMA request and the counted result. Thus, the ratio of the bus access frequency of DMA transfer to the bus access frequency of another bus master can equal to the ratio set in the register. Accordingly, a band which allows another bus master to use the bus during DMA transfer can be predicted. In addition, the value set in the register can be appropriately varied depending upon the urgency of DMA transfer, so that degradation of the performance of a system as a whole would not occur.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.